ARMSim# is a desktop application running in a Windows environment. It allows users to simulate the execution of ARM assembly language programs on a system based on the ARM7TDMI processor. ARMSim# has been developed by members of the Department of Computer Science at the University of Victoria, in Victoria, British Columbia, Canada. It is distributed for free for academic use. For commercial use, please contact the authors.
http://armsim.cs.uvic.ca/
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ARMSim | armsim.cs.uvic.ca Reviews
https://armsim.cs.uvic.ca
ARMSim# is a desktop application running in a Windows environment. It allows users to simulate the execution of ARM assembly language programs on a system based on the ARM7TDMI processor. ARMSim# has been developed by members of the Department of Computer Science at the University of Victoria, in Victoria, British Columbia, Canada. It is distributed for free for academic use. For commercial use, please contact the authors.
armsim.cs.uvic.ca
Use
http://armsim.cs.uvic.ca/Use.html
ARMSim# was developed as an effective simulator for the ARM processor to be used initially as a tool in academia, both for teaching and for research. It is similar in spirit to the SPIM software for the MIPS architecture. ARMSim# has been expanded to include features not normally found in such applications, such as cache simulation, detailed timing information and extensions to the ISA and user interface.
Downloads
http://armsim.cs.uvic.ca/Downloads.html
ARMSim# is a desktop application running in a Windows environment. It has also been tested for executing in Linux and in the MAC OS using Mono or Parallel. It allows users to simulate the execution of ARM assembly language programs on a system based on the ARM7TDMI processor, together with collecting statistics for execution and cache usage. For more detailed information read the features. ARMSim# has the great feature of being extensible through Plugins. For writing and including new plugins is provided.
Features
http://armsim.cs.uvic.ca/Features.html
Full ARM7 TDMI simulation engine. Instruction counting and cycle counting is provided. Support of Single-Stepping into/over code. Run at full speed, stopping either at program termination or at breakpoint or at user command. Restarting simulation or Reloading/Assembling from original files. Support of all exception modes. Support of all banked registers and SCPSR registers. FIQ/IRQ fully simulated and can be invoked by plugins. Support of Thumb instructions. Window states are saved on application exit.
FAQ
http://armsim.cs.uvic.ca/FAQ.html
Can I run ARMSim# on its own, without any Plugins for I/O? Yes, but a processor can be uninteresting when used in isolation; it is useful to be connected to I/O devicse for any useful programming is possible. This is where the Plugins come in. Can I have more than one Plugin for I/O active? Yes, one can have more than one active plugin, however the plugins must not request conflicting resources such as memory addresses. Where should plugins be installed? I cannot see the plugins - where are they? Plug-in...
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dreamlayers: April 2015
http://dreamlayers.blogspot.com/2015_04_01_archive.html
Thursday, April 30, 2015. Sleep and wake notifications with systemd. After I upgraded to Ubuntu 15.04 Vivid Vervet, the Audacious. Plugin I used to control a display device I built. Had a problem. Functionality related to sleep and wake didn't work anymore. That's because UPower doesn't handle sleep and wake anymore. Notification events instead come from systemd-logind. Posted by Boris Gjenero. Tuesday, April 28, 2015. CPUID HWMonitor 1.20 causes blue screens. 120 to troubleshoot a UPS problem, and I got...
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ARMSim
ARMSim# is a desktop application running in a Windows environment. It allows users to simulate the execution of ARM assembly language programs on a system based on the ARM7TDMI processor. ARMSim# has been developed by members of the Department of Computer Science at the University of Victoria, in Victoria, British Columbia, Canada. It is distributed for free for academic use. For commercial use, please contact the authors.
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